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Ordering number : EN*A0908
LC07422T
Overview
CMOS IC
Audio CODEC with Video Driver
The LC07422T is an audio CODEC that has a built-in speaker amplifier and headphone amplifier and incorporates a video driver. A 2-input line selector and ALC circuit are provided in the audio recording system. A speaker amplifier with EVR, headphone amplifier, and line output are provided in the playback system. A video driver that obviates the need for an output coupling capacitor is also included to enable AV playback processing with the single chip.
Features
* Audio systems can be configured using this single chip since almost all the audio system circuits are provided. * A video driver obviating the need for an output coupling capacitor is included. * A high-performance ALC/limiter circuit that meets a variety of different conditions is incorporated. * A wide range of different functions can be set using parameter settings.
Functions
* The input signals for the speaker amplifier and headphone amplifier can be selected (DAC or PGA output). * Power-down control of individual function block and be exercised. * COCEC ADC for the digital recording of analog input signals DAC for outputting analog signals from the digital playback data * De-emphasis filter * When Y/C video signals are input, composite signals can be generated, and 3-system driver signals can be output.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment.
O1007 TI IM No.A0908-1/10
LC07422T
Main Circuits
* Line selector * ALC/Limiter * EVR (analog volume) * type 16bit ADC/DAC * Headphone amplifier * Speaker amplifier * Video driver : 2 stereo inputs : 1 stereo circuit : 1 stereo circuit : 1 stereo circuit : 1 stereo circuit : 1 stereo circuit : 3 circuits (Y,C,V)
Power Supply Voltage
VDD(digital) VDDio(digital IO) VDDana(analog) VDDsp(speaker) VDDh1,VDDh2(analog) VDDv(video) =2.8V(2.6 to 3.2V) =1.8V(1.71 to 3.2V) =2.8V(2.6 to 3.2V) =2.8V(2.6 to 3.2V) =4.8V(4.5 to 5.5V) =2.8V(2.6 to 3.2V)
Package Dimensions
unit : mm (typ) 3296
12.0 10.0 48 49 33 32
0.5 10.0
64 1 0.5 (1.25)
(1.0)
17 16 0.2 0.15
1.2max
0.1
SANYO : TQFP64(10X10)
12.0
Pin Assignment
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 BEEPin SP_AMPin MIXout HPout_L HPout_R HPt_C VDDh1 Vref_H_C VSSh Lout_L Lout_R MONana_L MONana_R Lin2_L Lin1_L Lin1_R
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Lin2_R N.C. VSSana Vref_C VDDana VSSsub N.C. VDDadc VSSadc VSSdac VDDdac RESET_X MCLK LRCLK BCLK TESTin
LC07422T
SPn VDDsp VSSsp SPp N.C. CPref_C CPn VSScp CPp CPminus_O CPminus_I Yout VDDv Vout Cout SDCout
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VDDio VSS VDD SDin SCLK CS_X ADC_Dout DAC_Din
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VDDh2 VSSv Cin Yin HDin G_PORT2 G_PORT1 G_PORT0 Top view No.A0908-2/10
LC07422T
Pin Description
(Note) I/O: I=> input, Is=> Schmitt input, O=> output, IOs=> input/output
PIN No. Digital System 60 61 62 63 64 1 2 3 4 5 9 10 11 12 6 7 8 Analog system 13 14 17 18 19 21 22 23 24 26 27 29 32 33 34 35 36 37 38 40 42 43 44 I I O O O O O O O O I I O O O O I O IO IO O Yin Cin SDCout Cout Vout Yout CPminus_I CPminus_O CPp CPn CPref_C SPp SPn BEEPin SP_AMPin MIXout HPout_L HPout_R HPt_C Vref_H_C Lout_L Lout_R MONana_L Y signal input C signal input DC output for SDC signal C signal output Video signal output Y signal output Connect to CPminus O pin Reference voltage (minus) Connect an external capacitor Charge pump pin Connect an external capacitor Charge pump pin Connect an external capacitor Reference voltage Connect an external capacitor Speaker output Speaker output BEEP signal input Speaker amplifier input Mixing circuit (L+R) output Headphone output, Left channel Headphone output, Right channel Time constant setting Connect an external capacitor Reference voltage (4.8V system) Connect an external capacitor Line output, Left channel Line output, Right channel For IC testing (open in normal operation) Is I IOs IOs I Is O Is Is Is IOs IOs IOs Is RESET_X MCLK LRCLK BCLK TESTin DAC_Din ADC_Dout CS_X SCLK SDin G_PORT0 G_PORT1 G_PORT2 HDin VDD VSS VDDio Reset (negative polarity) Master Clock LR Clock (sample rate clock) Audio IF B Clock (serial data bit clock) Audio IF For IC testing (VSS fixed in normal operation) DAC serial data input Audio IF ADC serial data output Audio IF Chip select (negative polarity) Serial clock Microcontroller IF Serial data input Microcontroller IF For IC testing (open in normal operation) For IC testing (open in normal operation) For IC testing (open in normal operation) HD signal pulse input ( for test / Y signal clamp) Digital power supply Digital ground Digital IO power supply Microcontroller IF I/O Pin Name Description
Continued on next page.
No.A0908-3/10
LC07422T
Continued from preceding page.
PIN No. Analog system 45 46 47 48 49 52 15 16 20 25 30 31 39 41 51 53 54 56 57 58 59 O I I I I O MONana_R Lin2_L Lin1_L Lin1_R Lin2_R Vref_C VSSv VDDh2 VDDv VSScp VSSsp VDDsp VDDh1 VSSh VSSana VDDana VSSsub VDDadc VSSadc VSSdac VDDdac For IC testing (open in normal operation) Line input, Left channel 2 Line input, Left channel 1 Line input, Right channel 1 Line input, Right channel 2 Reference voltage (2.8V system) Analog ground for video driver 4.8V system analog power supply ( for SDC circuit) Analog power supply for video driver Ground for charge pump Speaker analog ground Speaker analog power supply 4.8V system analog power supply 4.8V system analog ground Analog ground Analog power supply Ground ADC analog power supply ADC analog ground DAC analog ground DAC analog power supply Connect an external capacitor I/O Pin Name Description
No.A0908-4/10
LC07422T
Block Diagram
Yin CLAM PGA LPF + Cin PGA LPF SDC Yout Vout Cout
HDin
SDCout to Speaker
BEEPin AMP control Vref_H_C VREF(VDDh/2) MIX EVR Selector Selector
SPp SPn SP_AMPin
Vref_C
VREF(VDDana/2)
MIXout to Headphone HPout_L
HPout_R HPt_C
Lout_L Lout_R
ALC/Limiter Lin1_L Lin2_L PGA ADC 16bit ALC cont. Lin1_R Lin2_R PGA ADC 16bit DAC 16bit InterFace DAC 16bit
MPU
MCLK BCLK LRCLK DAC_Din ADC_Dou t CS_X SCLK SDin
Divider I S IF
2
Serial IF/ Register
No.A0908-5/10
LC07422T
General specifications (* fs = sampling frequency)
Audio block * type 16-bit stereo ADC * type 16-bit stereo DAC * PGA for ALC/limiter * EVR (analog volume) : THD+N = 80dB (typ, with -1dBfs input) : THD+N = 80dB (typ, with 0dBfs input) : Amplifier gain => +34 to -14dB (in 0.5dB steps) : Amplifier gain => 0 to -65dB (The gain can be varied in steps from approx. 0.1 to 3.0dB; see characteristics diagram.) * Line output : Built-in pop noise suppression circuit * Speaker amplifier (monaural) : BTL drive, 250mW (3dBV, VDD = 2.8V, 8, THD+N = 1%) * Headphone amplifier : Output level => 2dBV (typ, 108, VDDh = 4.8V) * Sampling frequency : 48, 32kHz (44.1kHz supported by DAC only) * Audio data format I2S, left justification, right justification, BCLK: 64fs, 32fs, master/slave mode
Video block * No need for output coupling capacitor, no generation of V sag * LPF : fc = 8MHz * Amplifier gain : 6.5dB1.7dB, 0.1dB/step * 75 driver : 3 systems (Y, C, V) Common units * Master clock (MCLK pin input) : 256fs or 512fs, duty ratio = 50% (typ) * Microcontroller serial data format (register settings) : 3-line system (Chip select, clock, data) The maximum clock frequency is (1/4) MCLK. Video driver circuit [xxxx]: Resister setting
PGA Yin Cin HDin Vref(+aV) CPref_C +aV -aV SDCout SDC circuit CPn CPp CPminusO CPminusI Charge Pump [VD_SDC_SW] 11 10 01 00 SDCout Hi-Z VDDh 2.3V 0.0V CLAMP LPF LPF Vout Yout
+
Cout
Headphone amplifier circuit
HPout_L/HPout_R 100 H.P. 8 HPt_C
No.A0908-6/10
LC07422T
Outline of operation
1. System reset/power-down When the RESET_X pin is set to "VSS," the system is reset, and all the circuits go into the power-down mode. After the power is turned on, perform this operation once without fail. When the system is reset, the contents of the register are initialized. (See register tables.) For the subsequent startup of each function, refer to the section "Control/start/stop sequence for reducing pop noise." 2. ALC When the ALC is active, the PGA (programmable gain amplifier) gain value is automatically adjusted so that the audio level becomes the preset value. The PGA gain can be adjusted in a range from +34 to -14dB. By limiting the gain adjustment range to 0 to -14dB, this adjustment function can be made to work as a limiter function. The ALC operation can be stopped by a register setting. The ALC is then placed in the manual mode, and the PGA gain is adjusted by the register setting. For details, refer to the section "Description of ALC/limiter operation." 3. A/D converter The A/D converter converts the analog PGA output signals into digital data, and the digital data is then output as 16bit serial audio data. There are three formats supported: I2S, left justification and right justification. The A/D converter incorporates a high-pass filter for canceling DC offset. The analog input range of the ADC is 0.6VDDadc. When VDDadc is 2.8V, 0dBfs is 1.68V. 4. D/A converter The D/A converter converts the digital 16-bit serial audio data into analog signals. There are three formats supported: I2S, left justification and right justification. The D/A converter incorporates a high-pass filter for canceling DC offset. The analog input range of the ADC is 0.6VDDadc. When VDDadc is 2.8V, 0dBfs is 1.68V. 5. EVR This is an analog EVR. The gain can be set within a range from 0 dB to -65dB or mute (adjustable in steps). It is incorporated in the headphone and speaker amplifier path so that the output level of the headphones and speaker can be controlled separately from the line-out output. 6. Selector This selector is for selecting either the DAC or PGA output of the ALC. When the DAC output has been selected, the DAC output signals are output as the speaker amplifier and headphone amplifier output signals. When the PGA output has been selected, the signals from line input are all turned into analog signals to become the speaker amplifier and headphone amplifier output signals.
7. MIX This is the mixing circuit for the left- and right-channel audio signals. In other words, this functions as a monaural signal generator circuit to provide a monaural speaker amplifier input. The left- and right-channel signals are mixed on a 1:1 basis and then output through the -2dB amplifier. If the left- and right-channel signals are identical, the total gain becomes 4dB (= 6dB(doubled) -2dB). 8. SP AMP This is the monaural speaker amplifier. Its maximum output is 250mW (typ VDD =2.8V, 8, THD+N = 10%). Inputs to the amplifier are the audio signal SP_AMPin pin and BEEPin pin signals. For the BEEPin pin signal, the mixing can be set ON or OFF, and the gain level can be selected (from -21 to -12dB). A thermal shutdown function is provided. When it is left enabled, the speaker amplifier operation is automatically shut down when the chip temperature has reached a high level.
No.A0908-7/10
LC07422T
9. Video driver Negative power is generated by the charge pump circuit and supplied to the video driver. Therefore, the video driver operates on the positive and negative power supplies. The video signals are output with no DC components for the ground reference. As a result, with 75 termination, there is no need for an output coupling capacitor. In principle, no V sag is generated. 10. Register settings This is a 3-line system serial control circuit. The three lines are CS_X (Chip Select/low active), SCLK (Serial Clock) and SDin (Serial Data). Data can only be written into the register: The register data cannot be read out. The data transfer rate--in other words, the maximum SCLK frequency--depends on the MCLK pin clock. For details, refer to the section "Switching characteristics." 11. Master clock The master clock frequency is 256fs. This clock signal must be input from the MCLK pin. A frequency divider (1/2) incorporated so an input with a frequency of 512fs can also be supplied. 12. Audio data formats I2S, left justification and right justification modes are supported. It is possible to select master or slave mode for BCLK and LRCLK. For details, refer to the section "Audio data formats."
No.A0908-8/10
LC07422T
Register Table
ADRS(Address): displayed in hexadecimal notation, Init (initial value): displayed in hexadecimal notation "0" settings are used for registers indicated with "0". The shaded registers are for IC chip testing. Their initial values are fixed. Data must be set in all the registers. (The TEST1-8 addresses, including the registers for test purposes, are set in the sequence of 16 h to 1 Dh.)
Function ADRS [7:0] 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh Register Data D[7:0] INIT 7 00h 00h 11h 3Dh 86h 0Eh 0Eh 0Eh 04h 00h 00h A3h 80h 80h 2Eh 0Bh 01h 18h 11h 11h 30h 56h 00h 00h 00h 04h 00h 00h 01h 00h VREF_BIAS[1] SP_OUTEN 0 ALC_VAL[2] ALC_ZCD ALC_OFF ALC_MUTE_L ALC_MUTE_R TEST0[7] 0 DAC_INV SEL_L[1] EVR_MUTE_L EVR_MUTE_R 0 0 0 SP_EXTBP_EN 0 0 0 0 TEST1[7] TEST2[7] TEST3[7] TEST4[7] TEST5[7] TEST6[7] TEST7[7] TEST8[7] 6 VREF_BIAS[0] SP_PDX 0 ALC_VAL[1] ALC_ZCDTM[1] ALC_VMAX[6] ALC_DVL[6] ALC_DVR[6] TEST0[6] 0 ADC_INV SEL_L[0] 0 0 0 0 0 SP_EXTBP_G[1] 0 0 0 VD_CP_CLK[2] TEST1[6] TEST2[6] TEST3[6] TEST4[6] TEST5[6] TEST6[6] TEST7[6] TEST8[6] 5 SYNC_CLR MIX_PDX LI_SEL_L[2] ALC_VAL[0] ALC_ZCDTM[0] ALC_VMAX[5] ALC_DVL[5] ALC_DVR[5] TEST0[5] 0 0 SEL_R[1] EVR_GAIN_L[5] EVR_GAIN_R[5] EVR_ZCD 0 0 SP_EXTBP_G[0] VD_Y_GAIN[5] VD_C_GAIN[5] VD_SDC_SW[1] VD_CP_CLK[1] TEST1[5] TEST2[5] TEST3[5] TEST4[5] TEST5[5] TEST6[5] TEST7[5] TEST8[5] 4 SEL_PDX HP_PDX LI_SEL_L[1] ALC_FA[1] ALC_FULLEN ALC_VMAX[4] ALC_DVL[4] ALC_DVR[4] TEST0[4] ADF_BCLK DE_EN SEL_R[0] EVR_GAIN_L[4] EVR_GAIN_R[4] EVR_ZCDTM[1] 0 0 SP_TSD_EN VD_Y_GAIN[4] VD_C_GAIN[4] VD_SDC_SW[0] VD_CP_CLK[0] TEST1[4] TEST2[4] TEST3[4] TEST4[4] TEST5[4] TEST6[4] TEST7[4] TEST8[4] 3 ALC_PDX LO_PDX 0 ALC_FA[0] ALC_ATLIM[1] ALC_VMAX[3] ALC_DVL[3] ALC_DVR[3] TEST0[3] MCLK_DIV[1] ADF_FS[1] 0 EVR_GAIN_L[3] EVR_GAIN_R[3] EVR_ZCDTM[0] LO_GAIN[1] 0 SP_IDL[1] VD_Y_GAIN[3] VD_C_GAIN[3] 0 0 TEST1[3] TEST2[3] TEST3[3] TEST4[3] TEST5[3] TEST6[3] TEST7[3] TEST8[3] 2 ADC_A_PDX ADC_D_PDX 0 ALC_FR[2] ALC_ATLIM[0] ALC_VMAX[2] ALC_DVL[2] ALC_DVR[2] TEST0[2] MCLK_DIV[0] ADF_FS[0] 0 EVR_GAIN_L[2] EVR_GAIN_R[2] EVR_SOFTSW LO_GAIN[0] HP_PDNHIZ SP_IDL[0] VD_Y_GAIN[2] VD_C_GAIN[2] 0 VD_CLP_W TEST1[2] TEST2[2] TEST3[2] TEST4[2] TEST5[2] TEST6[2] TEST7[2] TEST8[2] 1 DAC_A_PDX DAC_D_PDX LI_SEL_R[2] ALC_FR[1] ALC_RWT[1] ALC_VMAX[1] ALC_DVL[1] ALC_DVR[1] TEST0[1] ADF_MODE[1] ADF_LB MIX_MONO[1] EVR_GAIN_L[1] EVR_GAIN_R[1] EVR_SSC[1] LO_VREFSW HP_REFEN SP_BIAS[1] VD_Y_GAIN[1] VD_C_GAIN[1] VD_V_EN VD_CLP_POS TEST1[1] TEST2[1] TEST3[1] TEST4[1] TEST5[1] TEST6[1] TEST7[1] TEST8[1] 0 VIDEO_PDX EVR_PDX LI_SEL_R[1] ALC_FR[0] ALC_RWT[0] ALC_VMAX[0] ALC_DVL[0] ALC_DVR[0] TEST0[0] ADF_MODE[0] ADF_MASTER MIX_MONO[0] EVR_GAIN_L[0] EVR_GAIN_R[0] EVR_SSC[0] LO_MUTE HP_MUTE SP_BIAS[0] VD_Y_GAIN[0] VD_C_GAIN[0] VD_YC_EN VD_TEST_CLP TEST1[0] TEST2[0] TEST3[0] TEST4[0] TEST5[0] TEST6[0] TEST7[0] TEST8[0]
PM1 PM2 ALC1 ALC2 ALC3 ALC4 ALC5 ALC6 TEST0 CODEC1 CODEC2 SEL/MIX EVR1 EVR2 EVR3 LINE HP SPK VIDEO1 VIDEO2 VIDEO3 VIDEO4 TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 TEST8
ADRS INIT PM ALC ADC DAC EVR ADF
=Address =Initial value =Power Management =Automatic Level Control =AD Converter =DA Converter =Electronic Variable Resistor =Audio Data Format
PGA Lch Rch 2^n Nh Nb ABC[n]
=Programmable Gain Amplifier =Left channel =Right channel =2n (ex. 2^10 = 1024) = N denotes a hexadecimal number. = N denotes a binary number. = Register with a multiple number of bits. ABC is the register name, and "n" is the number of bits.
No.A0908-9/10
LC07422T
Microcontroller Serial Interface
The internal registers values are written by the serial interface consisting of the three CS_X, SCLK, and SDin lines. When the CS_X pin is set low, the LC07422T is switched into the mode that enables operation. The data is received on a byte basis with MSB first. Continuous access (burst access) is also possible, and the addresses incremented by 1 are accessed in sequence with each byte following access to the register specified by the address byte. If the size of data exceeding the highest address (1D) is accessed in this process, the data concerned is treated as invalid. In other word, the address never wraps around to 00 (HEX). The maximum data transfer rate (maximum SCLK frequency) depends on the MCLK pin clock. Refer to the section "Switching characteristics." * Transferring data to one address: Data (D) is written in address (A)
A[7:0] D[7:0] X CS_X SCLK SDin X X A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] ADDRESS BYTE D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] WRITE DATA (address A) X X : Designated address : Register data : Invalid
* Transferring data to contiguous addresses: Data (D0) is written in address (A), and data (D1) is written into address (A+1).
CS_X SCLK SDin X X
A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] D0[7] D0[6] D0[5] D0[4] D0[3] D0[2] D0[1] D0[0] D1[7] D1[6] D1[5] D1[4] D1[3] D1[2] D1[1] D1[0] Dn[0]
X X
ADDRESS BYTE
WRITE DATA (address A)
WRITE DATA (address A+1)
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This catalog provides information as of October, 2007. Specifications and information herein are subject to change without notice.
PS No.A0908-10/10

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